// Copyright (C) 1953-2022 NUDT
// Verilog module name - command_parse_and_encapsulate_clt
// Version: V4.0.0.20220526
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module command_parse_and_encapsulate_clt
(
        i_clk                       ,       
        i_rst_n                     ,      
                                    
        iv_addr                     ,         
        iv_wdata                    ,         
        i_wr                        ,      
        i_rd                        ,        
                                    
        o_wr                        ,      
        ov_addr                     ,      
        ov_rdata                    ,      
                          
        ov_flowidram_addr           ,      
        ov_flowidram_wdata          ,      
        o_flowidram_wr              ,      
        iv_flowidram_rdata          ,      
        o_flowidram_rd              ,

        ov_dmacram_addr             ,
        ov_dmacram_wdata            ,
        o_dmacram_wr                ,
        iv_dmacram_rdata            ,
        o_dmacram_rd                ,  

        ov_ipram_addr_cpe2ram                   ,
        ov_ipram_wdata_cpe2ram                  ,
        o_ipram_wr_cpe2ram                      ,
        o_ipram_rd_cpe2ram                      ,
        iv_ipram_rdata_ram2cpe                  ,

        ov_droute_portbm_cpe2tlp                ,
        ov_sroute_portbm_cpe2tlp                ,
        o_unknown_multicast_forwardmode_cpe2tlp ,


        ov_fwdmoderam_addr          ,
        ov_fwdmoderam_wdata         ,
        o_fwdmoderam_wr             ,
        iv_fwdmoderam_rdata         ,
        o_fwdmoderam_rd             ,

        ov_broadcast_storm_prevent_outport,
        
        o_hit_cnt_clr            ,
                          
        iv_entry0_hit_cnt   ,
        iv_entry1_hit_cnt   ,
        iv_entry2_hit_cnt   ,
        iv_entry3_hit_cnt   ,
        iv_entry4_hit_cnt   ,
        iv_entry5_hit_cnt   ,
        iv_entry6_hit_cnt   ,
        iv_entry7_hit_cnt  ,
        iv_entry8_hit_cnt ,       
        iv_entry9_hit_cnt ,       
        iv_entry10_hit_cnt,       
        iv_entry11_hit_cnt,       
        iv_entry12_hit_cnt,       
        iv_entry13_hit_cnt,       
        iv_entry14_hit_cnt,       
        iv_entry15_hit_cnt,       
        iv_entry16_hit_cnt,       
        iv_entry17_hit_cnt,       
        iv_entry18_hit_cnt,       
        iv_entry19_hit_cnt,       
        iv_entry20_hit_cnt,       
        iv_entry21_hit_cnt,       
        iv_entry22_hit_cnt,       
        iv_entry23_hit_cnt,       
        iv_entry24_hit_cnt,       
        iv_entry25_hit_cnt,       
        iv_entry26_hit_cnt,       
        iv_entry27_hit_cnt,       
        iv_entry28_hit_cnt,       
        iv_entry29_hit_cnt,       
        iv_entry30_hit_cnt,       
        iv_entry31_hit_cnt,       
        iv_entry32_hit_cnt,       
        iv_entry33_hit_cnt,       
        iv_entry34_hit_cnt,       
        iv_entry35_hit_cnt,       
        iv_entry36_hit_cnt,       
        iv_entry37_hit_cnt,       
        iv_entry38_hit_cnt,       
        iv_entry39_hit_cnt,       
        iv_entry40_hit_cnt,       
        iv_entry41_hit_cnt,       
        iv_entry42_hit_cnt,       
        iv_entry43_hit_cnt,       
        iv_entry44_hit_cnt,       
        iv_entry45_hit_cnt,       
        iv_entry46_hit_cnt,       
        iv_entry47_hit_cnt,       
        iv_entry48_hit_cnt,       
        iv_entry49_hit_cnt,       
        iv_entry50_hit_cnt,       
        iv_entry51_hit_cnt,       
        iv_entry52_hit_cnt,       
        iv_entry53_hit_cnt,       
        iv_entry54_hit_cnt,       
        iv_entry55_hit_cnt,       
        iv_entry56_hit_cnt,       
        iv_entry57_hit_cnt,       
        iv_entry58_hit_cnt,       
        iv_entry59_hit_cnt,       
        iv_entry60_hit_cnt,       
        iv_entry61_hit_cnt,       
        iv_entry62_hit_cnt,       
        iv_entry63_hit_cnt         
);

// I/O
// clk & rst
input                   i_clk;
input                   i_rst_n;

input       [18:0]      iv_addr;                         
input       [31:0]      iv_wdata;                        
input                   i_wr;         
input                   i_rd;         

output reg              o_wr              ;
output reg [18:0]       ov_addr           ;
output reg [31:0]       ov_rdata          ;
//configuration 
output reg [13:0]       ov_flowidram_addr    ;   
output reg [73:0]       ov_flowidram_wdata   ;  
output reg              o_flowidram_wr       ;   
input      [73:0]       iv_flowidram_rdata   ;  
output reg              o_flowidram_rd       ;
reg                     r_flowidram_addr_high_or_low;

output reg [5:0]        ov_dmacram_addr    ;   
output reg [81:0]       ov_dmacram_wdata   ;  
output reg              o_dmacram_wr       ;   
input      [81:0]       iv_dmacram_rdata   ;  
output reg              o_dmacram_rd       ;  
reg        [1:0]        rv_dmacram_addr_high_or_low    ; 

output  reg    [2:0]       ov_ipram_addr_cpe2ram                   ;
output  reg    [64:0]      ov_ipram_wdata_cpe2ram                  ;
output  reg                o_ipram_wr_cpe2ram                      ;
output  reg                o_ipram_rd_cpe2ram                      ;
input  wire    [64:0]      iv_ipram_rdata_ram2cpe                  ;
reg            [1:0]       rv_ipram_addr_high_or_low                ;

output  reg    [31:0]      ov_droute_portbm_cpe2tlp                ;
output  reg    [31:0]      ov_sroute_portbm_cpe2tlp                ;
output  reg                o_unknown_multicast_forwardmode_cpe2tlp ;

output reg [5:0]        ov_fwdmoderam_addr           ;   
output reg [33:0]       ov_fwdmoderam_wdata          ;  
output reg              o_fwdmoderam_wr              ;   
input      [33:0]       iv_fwdmoderam_rdata          ;  
output reg              o_fwdmoderam_rd              ;
reg                     r_fwdmoderam_addr_high_or_low;

output reg [32:0]       ov_broadcast_storm_prevent_outport;
output reg              o_hit_cnt_clr            ;
                 
input      [15:0]       iv_entry0_hit_cnt ;
input      [15:0]       iv_entry1_hit_cnt ;
input      [15:0]       iv_entry2_hit_cnt ;
input      [15:0]       iv_entry3_hit_cnt ;
input      [15:0]       iv_entry4_hit_cnt ;
input      [15:0]       iv_entry5_hit_cnt ;
input      [15:0]       iv_entry6_hit_cnt ;
input      [15:0]       iv_entry7_hit_cnt ;
input      [15:0]       iv_entry8_hit_cnt ;      
input      [15:0]       iv_entry9_hit_cnt ;      
input      [15:0]       iv_entry10_hit_cnt;      
input      [15:0]       iv_entry11_hit_cnt;      
input      [15:0]       iv_entry12_hit_cnt;      
input      [15:0]       iv_entry13_hit_cnt;      
input      [15:0]       iv_entry14_hit_cnt;      
input      [15:0]       iv_entry15_hit_cnt;      
input      [15:0]       iv_entry16_hit_cnt;      
input      [15:0]       iv_entry17_hit_cnt;      
input      [15:0]       iv_entry18_hit_cnt;      
input      [15:0]       iv_entry19_hit_cnt;      
input      [15:0]       iv_entry20_hit_cnt;      
input      [15:0]       iv_entry21_hit_cnt;      
input      [15:0]       iv_entry22_hit_cnt;      
input      [15:0]       iv_entry23_hit_cnt;      
input      [15:0]       iv_entry24_hit_cnt;      
input      [15:0]       iv_entry25_hit_cnt;      
input      [15:0]       iv_entry26_hit_cnt;      
input      [15:0]       iv_entry27_hit_cnt;      
input      [15:0]       iv_entry28_hit_cnt;      
input      [15:0]       iv_entry29_hit_cnt;      
input      [15:0]       iv_entry30_hit_cnt;      
input      [15:0]       iv_entry31_hit_cnt;      
input      [15:0]       iv_entry32_hit_cnt;      
input      [15:0]       iv_entry33_hit_cnt;      
input      [15:0]       iv_entry34_hit_cnt;      
input      [15:0]       iv_entry35_hit_cnt;      
input      [15:0]       iv_entry36_hit_cnt;      
input      [15:0]       iv_entry37_hit_cnt;      
input      [15:0]       iv_entry38_hit_cnt;      
input      [15:0]       iv_entry39_hit_cnt;      
input      [15:0]       iv_entry40_hit_cnt;      
input      [15:0]       iv_entry41_hit_cnt;      
input      [15:0]       iv_entry42_hit_cnt;      
input      [15:0]       iv_entry43_hit_cnt;      
input      [15:0]       iv_entry44_hit_cnt;      
input      [15:0]       iv_entry45_hit_cnt;      
input      [15:0]       iv_entry46_hit_cnt;      
input      [15:0]       iv_entry47_hit_cnt;      
input      [15:0]       iv_entry48_hit_cnt;      
input      [15:0]       iv_entry49_hit_cnt;      
input      [15:0]       iv_entry50_hit_cnt;      
input      [15:0]       iv_entry51_hit_cnt;      
input      [15:0]       iv_entry52_hit_cnt;      
input      [15:0]       iv_entry53_hit_cnt;      
input      [15:0]       iv_entry54_hit_cnt;      
input      [15:0]       iv_entry55_hit_cnt;      
input      [15:0]       iv_entry56_hit_cnt;      
input      [15:0]       iv_entry57_hit_cnt;      
input      [15:0]       iv_entry58_hit_cnt;      
input      [15:0]       iv_entry59_hit_cnt;      
input      [15:0]       iv_entry60_hit_cnt;      
input      [15:0]       iv_entry61_hit_cnt;      
input      [15:0]       iv_entry62_hit_cnt;      
input      [15:0]       iv_entry63_hit_cnt;

reg                     r_cfg_hit_cnt_clr;    
always@(posedge i_clk or negedge i_rst_n)begin
    if(!i_rst_n) begin
        ov_flowidram_addr            <= 14'b0  ;
        ov_flowidram_wdata           <= 74'b0  ;
        o_flowidram_wr               <= 1'b0   ;
        o_flowidram_rd               <= 1'b0   ;
        r_flowidram_addr_high_or_low <= 1'b0;
        
        ov_dmacram_addr              <= 6'b0    ;
        ov_dmacram_wdata             <= 82'b0   ;
        o_dmacram_wr                 <= 1'b0    ;
        o_dmacram_rd                 <= 1'b0    ;
        rv_dmacram_addr_high_or_low  <= 2'b0    ;
        
        ov_ipram_addr_cpe2ram        <= 3'b0    ;
        ov_ipram_wdata_cpe2ram       <= 65'b0   ;
        o_ipram_wr_cpe2ram           <= 1'b0    ;
        o_ipram_rd_cpe2ram           <= 1'b0    ;
        rv_ipram_addr_high_or_low    <= 2'b0    ;

        ov_droute_portbm_cpe2tlp                <= 32'b0;
        ov_sroute_portbm_cpe2tlp                <= 32'b0;
        o_unknown_multicast_forwardmode_cpe2tlp <= 1'b0;
        
        ov_fwdmoderam_addr           <= 6'b0    ;
        ov_fwdmoderam_wdata          <= 34'b0   ;
        o_fwdmoderam_wr              <= 1'b0    ;
        o_fwdmoderam_rd              <= 1'b0    ;
        r_fwdmoderam_addr_high_or_low<= 1'b0    ;
          
        ov_broadcast_storm_prevent_outport  <= 33'h0;//33'h1_ffff_ffff;
        
        o_hit_cnt_clr              <= 1'b0;
        r_cfg_hit_cnt_clr          <= 1'b0;
    end
    else begin
        if(i_wr)begin//write
            if((iv_addr <= 19'h07fff))begin//tsn forward table                       
                if(!iv_addr[0])begin
                    ov_flowidram_wdata[63:32]     <= iv_wdata[31:0]   ;//outport
                end
                else begin
                    ov_flowidram_wdata[31:0]      <= iv_wdata[31:0]   ; 
                    ov_flowidram_wdata[73:64]     <= iv_wdata[9:0]    ;//validslot                
                end
                ov_flowidram_addr      <= iv_addr[14:1]   ;
                o_flowidram_wr         <= iv_addr[0]            ;
                o_flowidram_rd         <= 1'b0            ;
                
                ov_dmacram_addr        <= 6'b0            ;
                o_dmacram_wr           <= 1'b0            ;
                o_dmacram_rd           <= 1'b0            ;

                ov_ipram_addr_cpe2ram        <= 3'b0    ;
                ov_ipram_wdata_cpe2ram       <= 65'b0   ;
                o_ipram_wr_cpe2ram           <= 1'b0    ;
                o_ipram_rd_cpe2ram           <= 1'b0    ;
                
                ov_fwdmoderam_addr     <= 6'b0    ;
                o_fwdmoderam_wr        <= 1'b0    ;
                o_fwdmoderam_rd        <= 1'b0    ;                
                
                o_hit_cnt_clr          <= 1'b0            ; 
            end
            else if(((iv_addr >= 19'h08000)&&(iv_addr <= 19'h080ff)))begin//mac forward table
                if(iv_addr[1:0] == 2'h0)begin
                    ov_dmacram_wdata[81]       <= iv_wdata[31] ;//valid
                    ov_dmacram_wdata[80:64]    <= iv_wdata[16:0] ;//outport[32:16]
                    ov_dmacram_wdata[63:0]     <= ov_dmacram_wdata[63:0] ; 
                    o_dmacram_wr               <= 1'b0           ;
                end
                else if(iv_addr[1:0] == 2'h1)begin
                    ov_dmacram_wdata[81:64]    <= ov_dmacram_wdata[81:64] ; 
                    ov_dmacram_wdata[63:48]    <= iv_wdata[31:16] ;//outport[15:0]
                    ov_dmacram_wdata[47:32]    <= iv_wdata[15:0] ;//dmac[47:32]
                    o_dmacram_wr               <= 1'b0           ;
                end 
                else if(iv_addr[1:0] == 2'h2)begin
                    ov_dmacram_wdata[81:32]    <= ov_dmacram_wdata[81:32] ; 
                    ov_dmacram_wdata[31:0]     <= iv_wdata[31:0] ;//dmac[31:0]
                    o_dmacram_wr               <= 1'b0           ;
                end                 
                else begin
                    ov_dmacram_wdata           <= ov_dmacram_wdata ; 
                    o_dmacram_wr               <= 1'b1           ;
                end
                ov_dmacram_addr     <= iv_addr[7:2]                            ;
                o_dmacram_rd        <= 1'b0                                    ;  
                                                                                              
                ov_flowidram_addr      <= 14'b0           ;
                o_flowidram_wr         <= 1'b0            ;
                o_flowidram_rd         <= 1'b0            ; 

                ov_ipram_addr_cpe2ram        <= 3'b0    ;
                ov_ipram_wdata_cpe2ram       <= 65'b0   ;
                o_ipram_wr_cpe2ram           <= 1'b0    ;
                o_ipram_rd_cpe2ram           <= 1'b0    ;

                ov_fwdmoderam_addr     <= 6'b0    ;
                o_fwdmoderam_wr        <= 1'b0    ;
                o_fwdmoderam_rd        <= 1'b0    ;                  
              
                o_hit_cnt_clr          <= 1'b0            ;                 
            end
            else if((iv_addr == 19'h09000))begin//o_hit_cnt_clr
                o_hit_cnt_clr              <= iv_wdata[0]     ; 
                r_cfg_hit_cnt_clr          <= iv_wdata[0]     ;
            end
            else if(iv_addr == 19'h09022)begin//ov_broadcast_storm_prevent_outport
                ov_broadcast_storm_prevent_outport[32]    <= iv_wdata[0]   ;
            end
            else if(iv_addr == 19'h09023)begin//ov_broadcast_storm_prevent_outport
                ov_broadcast_storm_prevent_outport[31:0]  <= iv_wdata[31:0]   ;
            end
            
            /************** new code:20240126 *****************/
            else if (iv_addr == 19'h09024) begin
                ov_droute_portbm_cpe2tlp <= iv_wdata;
            end
            else if (iv_addr == 19'h09025) begin
                ov_sroute_portbm_cpe2tlp <= iv_wdata;
            end
            else if (iv_addr == 19'h09026) begin
                o_unknown_multicast_forwardmode_cpe2tlp <= iv_wdata[0];
            end
            /***************** end of new code ****************/ 

            else if(((iv_addr >= 19'h10000)&&(iv_addr <= 19'h1003f)))begin//forward mode table
                if(!iv_addr[0])begin
                    ov_fwdmoderam_wdata[33]     <= iv_wdata[31]     ;//valid
                    ov_fwdmoderam_wdata[32]     <= 1'b1             ;//stored forward to hcp.
                end
                else begin
                    ov_fwdmoderam_wdata[31:0]   <= iv_wdata[31:0]   ;               
                end
                ov_fwdmoderam_addr      <= iv_addr[6:1]    ;
                o_fwdmoderam_wr         <= iv_addr[0]      ;
                o_fwdmoderam_rd         <= 1'b0            ;

                ov_flowidram_addr       <= 14'b0           ;
                o_flowidram_wr          <= 1'b0            ;
                o_flowidram_rd          <= 1'b0            ;
                                        
                ov_dmacram_addr         <= 6'b0            ;
                o_dmacram_wr            <= 1'b0            ;
                o_dmacram_rd            <= 1'b0            ;

                ov_ipram_addr_cpe2ram        <= 3'b0    ;
                ov_ipram_wdata_cpe2ram       <= 65'b0   ;
                o_ipram_wr_cpe2ram           <= 1'b0    ;
                o_ipram_rd_cpe2ram           <= 1'b0    ;
                                        
                o_hit_cnt_clr           <= 1'b0            ;                
            end       

            /************************ new code:20240126 ****************************/
            else if (((iv_addr >= 19'h20000)&&(iv_addr <= 19'h2001F))) begin
                if (iv_addr[1:0] == 2'b00) begin
                    ov_ipram_addr_cpe2ram           <= iv_addr[4:2]    ;
                    ov_ipram_wdata_cpe2ram[64]      <= iv_wdata[31]   ;
                    o_ipram_wr_cpe2ram              <= 1'b0    ;
                end else if (iv_addr[1:0] == 2'b01) begin
                    ov_ipram_addr_cpe2ram           <= iv_addr[4:2]    ;
                    ov_ipram_wdata_cpe2ram[63:32]   <= iv_wdata   ;
                    o_ipram_wr_cpe2ram              <= 1'b0    ;
                end else if (iv_addr[1:0] == 2'b10) begin
                    ov_ipram_addr_cpe2ram           <= iv_addr[4:2]    ;
                    ov_ipram_wdata_cpe2ram[31:0]    <= iv_wdata   ;
                    o_ipram_wr_cpe2ram              <= 1'b0    ;
                end else begin
                    ov_ipram_addr_cpe2ram           <= iv_addr[4:2]    ;
                    ov_ipram_wdata_cpe2ram          <= ov_ipram_wdata_cpe2ram   ;
                    o_ipram_wr_cpe2ram              <= 1'b1   ;
                end
                o_ipram_rd_cpe2ram     <= 1'b0;

                ov_dmacram_addr        <= 6'b0             ;
                o_dmacram_wr           <= 1'b0             ;
                o_dmacram_rd           <= 1'b0             ;
                
                ov_flowidram_addr      <= 14'b0            ;
                o_flowidram_wr         <= 1'b0             ;
                o_flowidram_rd         <= 1'b0             ;

                ov_fwdmoderam_addr     <= 6'b0    ;
                o_fwdmoderam_wr        <= 1'b0    ;
                o_fwdmoderam_rd        <= 1'b0    ;                  

                o_hit_cnt_clr          <= 1'b0             ;    
            end
            /*************************** end of new code ************************/                
            else begin                  
                ov_flowidram_addr       <= 14'b0           ;
                o_flowidram_wr          <= 1'b0            ;
                o_flowidram_rd          <= 1'b0            ;
                                                           
                ov_dmacram_addr         <= 6'b0            ;
                o_dmacram_wr            <= 1'b0            ;
                o_dmacram_rd            <= 1'b0            ; 

                ov_ipram_addr_cpe2ram        <= 3'b0    ;
                ov_ipram_wdata_cpe2ram       <= 65'b0   ;
                o_ipram_wr_cpe2ram           <= 1'b0    ;
                o_ipram_rd_cpe2ram           <= 1'b0    ;

                ov_fwdmoderam_addr     <= 6'b0    ;
                o_fwdmoderam_wr        <= 1'b0    ;
                o_fwdmoderam_rd        <= 1'b0    ;                  
                                        
                o_hit_cnt_clr           <= 1'b0            ;                 
            end
        end
        else if(i_rd)begin//read
            if((iv_addr <= 19'h07fff))begin//tsn forward table
                ov_flowidram_addr       <= iv_addr[14:1]   ;
				r_flowidram_addr_high_or_low <= iv_addr[0];
                o_flowidram_wr          <= 1'b0            ;
                o_flowidram_rd          <= 1'b1            ;
                
                ov_dmacram_addr         <= 6'b0            ;
                o_dmacram_wr            <= 1'b0            ;
                o_dmacram_rd            <= 1'b0            ;

                ov_ipram_addr_cpe2ram        <= 3'b0    ;
                ov_ipram_wdata_cpe2ram       <= 65'b0   ;
                o_ipram_wr_cpe2ram           <= 1'b0    ;
                o_ipram_rd_cpe2ram           <= 1'b0    ;

                ov_fwdmoderam_addr     <= 6'b0    ;
                o_fwdmoderam_wr        <= 1'b0    ;
                o_fwdmoderam_rd        <= 1'b0    ;                  

                o_hit_cnt_clr           <= 1'b0            ;                 
            end
            else if(((iv_addr >= 19'h08000)&&(iv_addr <= 19'h080ff)))begin//mac forward table
                ov_dmacram_addr        <= iv_addr[7:2]     ;
                rv_dmacram_addr_high_or_low <= iv_addr[1:0]; 
                o_dmacram_wr           <= 1'b0             ;
                o_dmacram_rd           <= 1'b1             ;  
                                                                    
                ov_flowidram_addr      <= 14'b0            ;
                o_flowidram_wr         <= 1'b0             ;
                o_flowidram_rd         <= 1'b0             ; 

                ov_ipram_addr_cpe2ram        <= 3'b0    ;
                ov_ipram_wdata_cpe2ram       <= 65'b0   ;
                o_ipram_wr_cpe2ram           <= 1'b0    ;
                o_ipram_rd_cpe2ram           <= 1'b0    ;

                ov_fwdmoderam_addr     <= 6'b0    ;
                o_fwdmoderam_wr        <= 1'b0    ;
                o_fwdmoderam_rd        <= 1'b0    ;                  

                o_hit_cnt_clr          <= 1'b0             ;                 
            end
            else if(((iv_addr >= 19'h10000)&&(iv_addr <= 19'h1003f)))begin//mac forward table
                ov_dmacram_addr         <= 6'b0            ;
                o_dmacram_wr            <= 1'b0            ;
                o_dmacram_rd            <= 1'b0            ;

                ov_ipram_addr_cpe2ram        <= 3'b0    ;
                ov_ipram_wdata_cpe2ram       <= 65'b0   ;
                o_ipram_wr_cpe2ram           <= 1'b0    ;
                o_ipram_rd_cpe2ram           <= 1'b0    ;
                                                                    
                ov_flowidram_addr      <= 14'b0            ;
                o_flowidram_wr         <= 1'b0             ;
                o_flowidram_rd         <= 1'b0             ; 

                ov_fwdmoderam_addr            <= iv_addr[6:1]   ;
                r_fwdmoderam_addr_high_or_low <= iv_addr[0];
                o_fwdmoderam_wr        <= 1'b0    ;
                o_fwdmoderam_rd        <= 1'b1    ;                  

                o_hit_cnt_clr          <= 1'b0             ;                 
            end  
            /************************ new code:20240126 ****************************/
            else if (((iv_addr >= 19'h20000)&&(iv_addr <= 19'h2001F))) begin
                ov_ipram_addr_cpe2ram        <= iv_addr[4:2]    ;
                ov_ipram_wdata_cpe2ram       <= 65'b0   ;
                o_ipram_wr_cpe2ram           <= 1'b0    ;
                o_ipram_rd_cpe2ram           <= 1'b1    ;
                rv_ipram_addr_high_or_low    <= iv_addr[1:0];
                
                ov_dmacram_addr        <= 6'b0             ;
                o_dmacram_wr           <= 1'b0             ;
                o_dmacram_rd           <= 1'b0             ;
                
                ov_flowidram_addr      <= 14'b0            ;
                o_flowidram_wr         <= 1'b0             ;
                o_flowidram_rd         <= 1'b0             ;

                ov_fwdmoderam_addr     <= 6'b0    ;
                o_fwdmoderam_wr        <= 1'b0    ;
                o_fwdmoderam_rd        <= 1'b0    ;                  

                o_hit_cnt_clr          <= 1'b0             ;  
            end
            /*************************** end of new code ************************/   
            else begin
                ov_dmacram_addr        <= 6'b0             ;
                o_dmacram_wr           <= 1'b0             ;
                o_dmacram_rd           <= 1'b0             ;

                ov_ipram_addr_cpe2ram        <= 3'b0    ;
                ov_ipram_wdata_cpe2ram       <= 65'b0   ;
                o_ipram_wr_cpe2ram           <= 1'b0    ;
                o_ipram_rd_cpe2ram           <= 1'b0    ;
                
                ov_flowidram_addr      <= 14'b0            ;
                o_flowidram_wr         <= 1'b0             ;
                o_flowidram_rd         <= 1'b0             ;

                ov_fwdmoderam_addr     <= 6'b0    ;
                o_fwdmoderam_wr        <= 1'b0    ;
                o_fwdmoderam_rd        <= 1'b0    ;                  

                o_hit_cnt_clr          <= 1'b0             ;                 
            end
        end
        else begin
            ov_dmacram_addr            <= 6'b0             ;
            o_dmacram_wr               <= 1'b0             ;
            o_dmacram_rd               <= 1'b0             ;

            ov_ipram_addr_cpe2ram        <= 3'b0    ;
            ov_ipram_wdata_cpe2ram       <= ov_ipram_wdata_cpe2ram; //65'b0   ;
            o_ipram_wr_cpe2ram           <= 1'b0    ;
            o_ipram_rd_cpe2ram           <= 1'b0    ;
            
            ov_flowidram_addr          <= 14'b0            ;
            o_flowidram_wr             <= 1'b0             ;
            o_flowidram_rd             <= 1'b0             ; 

            ov_fwdmoderam_addr         <= 6'b0             ;
            o_fwdmoderam_wr            <= 1'b0             ;
            o_fwdmoderam_rd            <= 1'b0             ;             
                                       
            o_hit_cnt_clr              <= 1'b0             ;             
        end        
    end
end

reg  [2:0]  rv_flowidram_rden;
reg  [14:0] rv_flowidram_raddr0;
reg  [14:0] rv_flowidram_raddr1;
reg  [14:0] rv_flowidram_raddr2;
always@(posedge i_clk or negedge i_rst_n)begin
    if(!i_rst_n) begin
        rv_flowidram_rden   <= 3'b0;
        rv_flowidram_raddr0 <= 15'b0;
        rv_flowidram_raddr1 <= 15'b0;
        rv_flowidram_raddr2 <= 15'b0;
    end
    else begin
        rv_flowidram_rden   <= {rv_flowidram_rden[1:0],o_flowidram_rd};
        rv_flowidram_raddr0 <= {ov_flowidram_addr,r_flowidram_addr_high_or_low};
        rv_flowidram_raddr1 <= rv_flowidram_raddr0;
        rv_flowidram_raddr2 <= rv_flowidram_raddr1;        
    end
end

reg  [2:0]  rv_dmacram_rden;
reg  [7:0]  rv_dmacram_raddr0;
reg  [7:0]  rv_dmacram_raddr1;
reg  [7:0]  rv_dmacram_raddr2;
always@(posedge i_clk or negedge i_rst_n)begin
    if(!i_rst_n) begin
        rv_dmacram_rden   <= 3'b0;
        rv_dmacram_raddr0 <= 8'b0;
        rv_dmacram_raddr1 <= 8'b0;
        rv_dmacram_raddr2 <= 8'b0;
    end
    else begin
        rv_dmacram_rden   <= {rv_dmacram_rden[1:0],o_dmacram_rd};
        rv_dmacram_raddr0 <= {ov_dmacram_addr,rv_dmacram_addr_high_or_low};
        rv_dmacram_raddr1 <= rv_dmacram_raddr0;
        rv_dmacram_raddr2 <= rv_dmacram_raddr1;        
    end
end

reg  [2:0]  rv_fwdmoderam_rden  ;
reg  [6:0]  rv_fwdmoderam_raddr0;
reg  [6:0]  rv_fwdmoderam_raddr1;
reg  [6:0]  rv_fwdmoderam_raddr2;
always@(posedge i_clk or negedge i_rst_n)begin
    if(!i_rst_n) begin
        rv_fwdmoderam_rden   <= 3'b0;
        rv_fwdmoderam_raddr0 <= 7'b0;
        rv_fwdmoderam_raddr1 <= 7'b0;
        rv_fwdmoderam_raddr2 <= 7'b0;
    end
    else begin
        rv_fwdmoderam_rden   <= {rv_fwdmoderam_rden[1:0],o_fwdmoderam_rd};
        rv_fwdmoderam_raddr0 <= {ov_fwdmoderam_addr,r_fwdmoderam_addr_high_or_low};
        rv_fwdmoderam_raddr1 <= rv_fwdmoderam_raddr0;
        rv_fwdmoderam_raddr2 <= rv_fwdmoderam_raddr1;        
    end
end

/************************ new code:20240126 ****************************/
reg  [2:0]  rv_ipram_rden;
reg  [4:0]  rv_ipram_raddr0;
reg  [4:0]  rv_ipram_raddr1;
reg  [4:0]  rv_ipram_raddr2;
always@(posedge i_clk or negedge i_rst_n)begin
    if(!i_rst_n) begin
        rv_ipram_rden    <= 3'b0;
        rv_ipram_raddr0 <= 5'b0;
        rv_ipram_raddr1 <= 5'b0;
        rv_ipram_raddr2 <= 5'b0;
    end
    else begin
        rv_ipram_rden    <= {rv_ipram_rden[1:0],o_ipram_rd_cpe2ram};
        rv_ipram_raddr0 <= {ov_ipram_addr_cpe2ram,rv_ipram_addr_high_or_low};
        rv_ipram_raddr1 <= rv_ipram_raddr0;
        rv_ipram_raddr2 <= rv_ipram_raddr1;        
    end
end
/*************************** end of new code ************************/   


always@(posedge i_clk or negedge i_rst_n)begin
    if(!i_rst_n) begin
        o_wr            <= 1'b0 ;
        ov_addr         <= 19'b0;
        ov_rdata        <= 32'b0;
    end
    else begin
        if(rv_flowidram_rden[2])begin//get data from ram
            o_wr            <= 1'b1;
            ov_addr         <= {4'b0,rv_flowidram_raddr2};
            if(rv_flowidram_raddr2[0])begin
                ov_rdata      <= iv_flowidram_rdata[31:0];
            end
            else begin//high 32bit
                ov_rdata      <= iv_flowidram_rdata[63:32];
            end
        end           
        else if(rv_dmacram_rden[2])begin
            o_wr            <= 1'b1;
            ov_addr         <= {12'b000_1000_0000,rv_dmacram_raddr2};
            if(rv_dmacram_raddr2[1:0] == 2'b00)begin
                ov_rdata[31]    <= iv_dmacram_rdata[81];//valid
                ov_rdata[30:17] <= 14'b0;
                ov_rdata[16:0]  <= iv_dmacram_rdata[80:64];//outport
            end
            else if(rv_dmacram_raddr2[1:0] == 2'b01)begin
                ov_rdata        <= iv_dmacram_rdata[63:32];//outport,dmac
            end
            else if(rv_dmacram_raddr2[1:0] == 2'b10)begin
                ov_rdata        <= iv_dmacram_rdata[31:0];//dmac
            end             
            else begin
                ov_rdata        <= 32'b0;
            end
        end
        /************************ new code:20240126 ****************************/
        else if (rv_ipram_rden[2]) begin
            o_wr            <= 1'b1;
            ov_addr         <= {14'b01_0000_0000_0000,rv_ipram_raddr2};
            if(rv_ipram_raddr2[1:0] == 2'b00)begin
                ov_rdata[31]    <= iv_ipram_rdata_ram2cpe[64];//valid
                ov_rdata[30:0] <= 31'b0;
            end
            else if(rv_ipram_raddr2[1:0] == 2'b01)begin
                ov_rdata        <= iv_ipram_rdata_ram2cpe[63:32];
            end
            else if(rv_ipram_raddr2[1:0] == 2'b10)begin
                ov_rdata        <= iv_ipram_rdata_ram2cpe[31:0];
            end             
            else begin
                ov_rdata        <= 32'b0;
            end
        end
        else if (i_rd && (iv_addr == 19'h09024)) begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= ov_droute_portbm_cpe2tlp;
        end
        else if (i_rd && (iv_addr == 19'h09025)) begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= ov_sroute_portbm_cpe2tlp;
        end
        else if (i_rd && (iv_addr == 19'h09026)) begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {18'b0,o_unknown_multicast_forwardmode_cpe2tlp};
        end
        /*************************** end of new code ************************/  
        else if(i_rd && (iv_addr == 19'h09000))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {31'b0,r_cfg_hit_cnt_clr};
        end       
        else if(i_rd && (iv_addr == 19'h09002))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry1_hit_cnt,iv_entry0_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h09003))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry3_hit_cnt,iv_entry2_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h09004))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry5_hit_cnt,iv_entry4_hit_cnt};
        end 
        else if(i_rd && (iv_addr == 19'h09005))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry7_hit_cnt,iv_entry6_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h09006))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry9_hit_cnt,iv_entry8_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h09007))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry11_hit_cnt,iv_entry10_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h09008))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry13_hit_cnt,iv_entry12_hit_cnt};
        end  
        else if(i_rd && (iv_addr == 19'h09009))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry15_hit_cnt,iv_entry14_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h0900a))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry17_hit_cnt,iv_entry16_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h0900b))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry19_hit_cnt,iv_entry18_hit_cnt};
        end    
        else if(i_rd && (iv_addr == 19'h0900c))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry21_hit_cnt,iv_entry20_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h0900d))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry23_hit_cnt,iv_entry22_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h0900e))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry25_hit_cnt,iv_entry24_hit_cnt};
        end    
        else if(i_rd && (iv_addr == 19'h0900f))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry27_hit_cnt,iv_entry26_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h09010))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry29_hit_cnt,iv_entry28_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h09011))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry31_hit_cnt,iv_entry30_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h09012))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry33_hit_cnt,iv_entry32_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h09013))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry35_hit_cnt,iv_entry34_hit_cnt};
        end    
        else if(i_rd && (iv_addr == 19'h09014))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry37_hit_cnt,iv_entry36_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h09015))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry39_hit_cnt,iv_entry38_hit_cnt};
        end  
        else if(i_rd && (iv_addr == 19'h09016))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry41_hit_cnt,iv_entry40_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h09017))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry43_hit_cnt,iv_entry42_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h09018))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry45_hit_cnt,iv_entry44_hit_cnt};
        end    
        else if(i_rd && (iv_addr == 19'h09019))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry47_hit_cnt,iv_entry46_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h0901a))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry49_hit_cnt,iv_entry48_hit_cnt};
        end  
        else if(i_rd && (iv_addr == 19'h0901b))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry51_hit_cnt,iv_entry50_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h0901c))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry53_hit_cnt,iv_entry52_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h0901d))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry55_hit_cnt,iv_entry54_hit_cnt};
        end    
        else if(i_rd && (iv_addr == 19'h0901e))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry57_hit_cnt,iv_entry56_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h0901f))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry59_hit_cnt,iv_entry58_hit_cnt};
        end 
        else if(i_rd && (iv_addr == 19'h09020))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry61_hit_cnt,iv_entry60_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h09021))begin
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {iv_entry63_hit_cnt,iv_entry62_hit_cnt};
        end
        else if(i_rd && (iv_addr == 19'h09022))begin//ov_broadcast_storm_prevent_outport
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= {31'b0,ov_broadcast_storm_prevent_outport[32]};            
        end
        else if(i_rd && (iv_addr == 19'h09023))begin//ov_broadcast_storm_prevent_outport
            o_wr            <= 1'b1 ;
            ov_addr         <= iv_addr;
            ov_rdata        <= ov_broadcast_storm_prevent_outport[31:0];            
        end 
        else if(rv_fwdmoderam_rden[2])begin//get data from ram
            o_wr            <= 1'b1;
            ov_addr         <= {2'b0,1'b1,9'b0,rv_fwdmoderam_raddr2};
            if(rv_fwdmoderam_raddr2[0])begin
                ov_rdata      <= iv_fwdmoderam_rdata[31:0];
            end
            else begin//high 32bit
                ov_rdata      <= {iv_fwdmoderam_rdata[33],31'b0};
            end
        end         
        else begin
            o_wr            <= 1'b0 ;
            ov_addr         <= 19'b0;
            ov_rdata        <= 32'b0;
        end        
    end
end       
endmodule